Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers, such as silicon dioxide and conductive paths or interconnects formed of conductive materials. Interconnects are usually formed by filling a conductive material in trenches etched into the dielectric interlayers. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in different layers can be electrically connected using vias or contacts. A metallization process can be used to fill such features, i.e., via openings, trenches, pad openings or contact holes with a conductive material.
Copper and copper alloys have recently received considerable attention as interconnect materials because of their superior electromigration and low resistivity characteristics. The preferred method of copper metallization is electroplating. The electroplating can be done using, for example, a conventional electrochemical deposition (ECD) technique. Standard electrochemical deposition techniques yield copper layers that deposit conformally over large features, such as features with widths larger than about five micrometers. FIG. 1A shows an exemplary substrate 10 having a copper layer 12 that is formed by electrochemical deposition techniques. The copper layer 12 fills small features 14 and the large features 16 in the substrate. Prior to the deposition, the interior of the features and an upper surface 18 of the substrate 10 are lined with a barrier layer 20 and an optional copper seed layer (not shown). During the early stages of the deposition, the small features 14 are quickly filled with copper. However, filling the large feature 16 takes time and, once done, results in an excess copper 22 over the upper surface 18 of the substrate 10. The excess copper 22 exhibits a characteristic surface topography including a bump 24 over the small features 14 and a recess 26 over the large feature 16. The height of such bumps may vary and is a strong function of the chemistry used for electroplating. Use of leveler additives in the plating chemistry formulation typically reduces the size of the bump.
After the deposition, the electroplated substrates are typically transferred to a separate material removal system, such as a CMP system, and the excess copper is planarized to physically isolate the copper within each individual feature, and thereby forming the metallic interconnect structure. In a subsequent planarization step carried out in the same material removal system, the barrier layer on the surface (which is typically conductive) is also removed so that metal-filled features are electrically isolated from each other. As stated before, the excess copper is typically planarized using a chemical mechanical polishing (CMP) process. However, the above described topography of the excess copper causes problems in CMP and introduces defects in the planarized end product, as will be described later.
In a standard CMP process, a three-step removal approach is typically used in a CMP tool having three stations with three different pads and chemistry delivery means. In the first step, which is carried out in the first station within the CMP tool, bulk copper is removed with a chemistry that is optimized for fast removal and good planarization. During this step, most of the copper layer is planarized and removed, leaving behind only about a 100-300 nm (nanometer) thick copper layer. For example, an incoming wafer with electroplated copper, as shown in FIG. 1A, may have an 800-1200 nm thick excess copper layer. During this first step, the bulk of this excess copper is removed, leaving behind a thin layer that is only about 100-300 nm thick. In the second step, which is carried out in the second station of the CMP tool, a chemistry with a lower copper removal rate is typically employed. This chemistry is optimized for good defect performance and selectivity with respect to the barrier film and the dielectric layer. During the third step of the process, the barrier layer at the top surface is removed at a third station on the CMP tool.
As exemplified in FIG. 1B, one common problem observed in this approach is that the first and second steps of the process cannot efficiently planarize the excess copper 22 with the bump 24. As a result, although copper in the large feature 16 is planarized, a residual copper 28 is still left over the dense and small features 14. At this point, if the process is continued to over-polish the copper and remove the residual copper 28 to avoid electrical shorts between the small features 14, the top portion 30 of the copper in the large feature is also removed. Conductive material removal from large features is a defect called “dishing,” which reduces the amount of conductive material in an interconnect line and negatively impacts the device performance. There may also be erosion in the dense areas due to this over-polishing step.
The standard interconnect process described above is costly and yields dishing and erosion defects in the interconnect structures, as described above. The overall integration process uses electroplating tools yielding substrates with copper layers, as depicted in FIG. 1A, and CMP tools that receive the substrates with these copper layers and remove the excess copper as described above. The cost of an interconnect fabrication process is mostly in the material removal steps, which are carried out at a material removal tool or station, such as a CMP tool. As the number of interconnect layers increase, the impact of CMP cost and the impact of dishing and erosion defects become more and more important. If, instead of the thick and topographic copper layer shown in FIG. 1A, a thin and flat copper layer could be provided by the plating tool, the CMP process could be greatly simplified, thereby reducing costs and minimizing defects.
From the foregoing, it is clear that there is a need for new processes and systems which provide copper layers so that defects caused during the overburden removal steps are reduced or eliminated and the overall cost is reduced.